The invention lies in the fields of integrated technology, semiconductor technology, and memory technology.
Ferroelectric materials have been investigated for some time with respect to their suitability for storage applications, that is for memory applications. Here, two variants are primarily being considered. Firstly, ferroelectric material can be used as a dielectric layer with a high dielectric constant in a capacitor of a DRAM memory cell configuration. Secondly, ferroelectric transistors have been proposed (see, for example, European patent EP 0 566 585 B1; H. N. Lee et al, Ext. Abstr. Int. Conf. SSDM, Hamatsu, 1997, pp. 382-83; I. P. Han et al, Integrated Ferroelectrics, 1998, Vol. 22, pp. 213-21), which have two source-drain regions, a channel region and a gate electrode, a layer of ferroelectric material being provided between the gate electrode and the channel region. The conductivity of these transistors depends on the state of polarization of the layer of ferroelectric material. Ferroelectric transistors of this type are suitable for use in nonvolatile memories. In this case, two different logic values of an item of digital information are associated with two different states of polarization of the layer of ferroelectric material. Further possible uses for such ferroelectric transistors are, for example, neural networks.
Since ferroelectric material which is arranged on the surface of a semiconductor substrate exhibits poor boundary surface properties, which exert a negative influence on the electrical properties of a ferroelectric transistor, it has been proposed to use an intermediate layer of SiO3 (See EP 0 566 585 B1), MgO, CeO2, ZrO2, SrTiO3, Y2O3(See H. N. Lee et al, Ext. Abstr. Int. Conf. SSDM, Hamatsu, 1997, pp. 382-383) or Si3N4(see, for example I. P. Han et al, Integrated Ferroelectrics, 1998, Vol. 22, pp 213-221) between the ferroelectric layer and the semiconductor substrate in a ferroelectric transistor. These materials are insulating, stable oxides, which produce a sufficiently good boundary surface between the ferroelectric layer and the surface of the semiconductor substrate.
Between the gate electrode and the semiconductor substrate acting as an electrode, the ferroelectric layer is polarized. As a result of the remanent polarization, an electric field is generated. If a value of about 10 xcexcc/cm2 is assumed for the remanent polarization of the ferroelectric layer, then, for an intermediate layer of SiO2 with ∈r=3.9, a value of about 29 MV/cm is calculated for the electric field strength. The electric field strength is calculated in accordance with the formula E="sgr"/(∈0xc2x7∈r), where E is the electric field strength and "sgr" is the remanent polarization. Since the breakdown field strength of SiO2 is only around 10 MV/cm, electric breakdown of the intermediate layer must therefore be expected. The values for the remanent polarization, in particular of SBT (SrBi2Ta2O9) or PZT (PbZrxPi1xe2x88x92xO2), lie above 10 xcexcC/cm2, and even when using a dielectric material with a higher dielectric content than SiO2, it is therefore necessary to expect that field strengths in a critical range will occur.
It is accordingly an object of the invention to provide a ferroelectric transistor and its utilization in a memory cell configuration, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for a ferroelectric transistor wherein breakdown of a dielectric layer between a ferroelectric layer and a semiconductor substrate is avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a ferroelectric transistor, comprising:
a substrate having a main surface;
a first source-drain region, a channel region, and a second source-drain region adjoining said main surface of said semiconductor substrate, with said channel region arranged between said first and second source-drain regions;
a dielectric layer covering at least said channel region and overlapping said first source-drain region;
a ferroelectric layer disposed on said dielectric layer and covering at least a part of said first source-drain region adjacent said channel region;
a first polarization electrode and a second polarization electrode disposed on said dielectric layer, with said ferroelectric layer arranged between said first and second polarization electrodes;
a gate electrode above a first area of said channel region;
said dielectric layer having a thickness above said first area less than a thickness above a second area of said channel region below said second polarization electrode; and
said dielectric layer having a thickness above said part of said first source-drain region adjoining said channel region dimensioned such that a remanent polarization of said ferroelectric layer, aligned parallel to said main surface of said substrate, produces compensation charges in said second area of said channel region.
The ferroelectric transistor is particularly suitable for use as a memory cell in a memory cell configuration.
The ferroelectric transistor comprises a first source-drain region, a channel region and a second source-drain region, which adjoin a main surface of a semiconductor substrate. Here, the channel region is arranged between the first source-drain region and the second source-drain region. A dielectric layer is provided, which covers at least the surface of the channel region and overlaps the surface of the first source-drain region. Arranged on the surface of the dielectric layer is a ferroelectric layer, which covers at least a part, adjacent to the channel region, of the first source-drain region.
Also arranged on the surface of the dielectric layer are a first polarization electrode and a second polarization electrode, between which the ferroelectric layer is arranged. A gate electrode is arranged on the surface of the dielectric layer, above an area of the first channel region.
The thickness of the dielectric layer above the first area, that is to say under the gate electrode, is lower than above a second area of the channel region, which is arranged under the second polarization electrode. The thickness of the dielectric layer above that part of the first source-drain region which adjoins the channel region and is covered by the ferroelectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned parallel to the main surface, produces compensation charges in the second area of the channel region.
Since a remanent polarization of the ferroelectric layer is aligned parallel to the main surface in the ferroelectric transistor, because of the first polarization electrode and the second polarization electrode, the electric field generated by the remanent polarization is likewise aligned parallel to the main surface. The compensation charges in the second area of the channel region are generated by the lateral stray field from the electric field, which is much lower than the electric field itself. Therefore, breakdown of the dielectric layer between the semiconductor substrate and the ferroelectric layer is reliably avoided.
Depending on the state of polarization of the ferroelectric layer, a different number of compensation charges is generated in the second area of the channel region. In order to store an item of digital information, the ferroelectric layer is switched into two different polarization states, one polarization state generating so many compensation charges in the second area that the second area conducts, while the other polarization state generates so few compensation charges that the second area of the channel region does not conduct. The ferroelectric transistor is controlled via the gate electrode, which controls the first area of the channel region. A check is made to see whether the ferroelectric transistor conducts, in this case the polarization of the ferroelectric layer is adequate for conductivity of the second area of the channel region, or whether the ferroelectric transistor does not conduct, in this case the state of polarization is inadequate for conductivity of the second area of the channel region.
The change in the state of polarization of the ferroelectric layer, which corresponds to writing or changing stored information, is carried out via the first polarization electrode and the second polarization electrode. In particular, the thickness of the dielectric layer above that part of the first source-drain region which adjoins the channel region is less than the thickness of the dielectric layer above the second area of the channel region and less than the dimension of the second area of the channel region parallel to the main surface. This ensures that the insulation of the dielectric layer above the second area is sufficiently good for compensation charges to accumulate in the second area of the channel and not on the surface of the dielectric layer.
In accordance with an added feature of the invention, the ferroelectric layer is arranged partly above the channel region. In this case, the thickness of the dielectric layer above a part of the channel region which adjoins the first source-drain region and above that part of the first source-drain region which adjoins the channel region is substantially the same. This configuration of the invention has the advantage that sufficient compensation charges are generated in the channel region, even in the case of a low lateral stray field.
With regard to a reduced space requirement of the ferroelectric transistor, it is advantageous to form the second polarization electrode and the gate electrode as a common electrode.
In accordance with an additional feature of the invention, the thickness of the dielectric layer underneath the first polarization electrode, which is arranged above the first source-drain region, and above that part of the first source-drain region which adjoins the channel region is substantially the same. In this configuration, the dimension perpendicular to the main surface of the boundary surface between the first polarization electrode and the ferroelectric layer is greater than between the second polarization electrode and the ferroelectric layer. As a result, the electric stray field that acts in the second area of the channel region is increased.
In accordance with another feature of the invention, the thickness of the dielectric layer underneath the first polarization electrode and underneath the second polarization electrode is substantially the same. As a result, the dimension perpendicular to the main surface of the boundary surface between the first polarization electrode and the ferroelectric layer and the second polarization electrode and the ferroelectric layer is substantially the same, which is advantageous with respect to the production of the ferroelectric transistor.
In accordance with a concomitant feature of the invention, the dielectric layer comprises a first dielectric layer and a second dielectric layer. The first dielectric layer is in this case arranged on the main surface. The second dielectric layer is arranged above it. The second dielectric layer has an opening in the area of the gate electrode, so that the gate electrode is arranged on the surface of the first dielectric layer. The first dielectric layer thus corresponds to the gate dielectric of the ferroelectric transistor. This configuration has the advantage that the first dielectric layer can be optimized with respect to its characteristics as a gate dielectric, while the second dielectric layer represents the boundary surface to the ferroelectric layer and can be optimized with respect to the latter. The first dielectric layer preferably contains SiO2, CeO2, ZrO2 or Ta2O5 and has a thickness between 3.5 nm and 20 nm. The second dielectric layer preferably contains Si3N4, CeO2 or another selectively etchable dielectric material and, above the second area of the channel region has a thickness between 10 nm and 500 nm and, above that part of the first source-drain region which adjoins the channel region, has a thickness between 10 nm and 300 nm. The second dielectric layer can also contain nonselectively etchable dielectric material, if the selective etchability is of lower importance for production. With regard to possible degradation of the ferroelectric layer, it is advantageous to form the second dielectric layer as an air gap or vacuum area. For this purpose, an auxiliary structure is produced, which is etched out again after the adjacent structures have been finished.
The ferroelectric layer can contain all ferroelectric materials which are suitable for a ferroelectric transistor. In particular, the ferroelectric layer contains SBT (SrBi2Ta2O9), PZT (PbZrxTi1xe2x88x92xO2) or BMF (BaMgF4).
All substrates which are considered for the production of integrated circuits are suitable as a semiconductor substrate. In particular, the semiconductor substrate can be a monocrystalline silicon wafer, an SOI substrate, an SiGe substrate or a III-V semiconductor.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a ferroelectric transistor and its use in a memory cell configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.